There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever increasing reduction in size and separation between devices (e.g., capacitors) of an integrated circuit (IC) in order to reduce IC size and/or increase density. As capacitor size decreases, it becomes more difficult to sustain sufficient charge for the intended use of the capacitor as well as store the charge for a sufficient period of time.
FIG. 1 illustrates a conventional stacked capacitor structure 20 fabricated on a semiconductor substrate 22. The structure 20 includes a first electrode 24 and second electrode 26, and a capacitor dielectric 28 interposed therebetween. In fabricating this structure, typically, a first dielectric layer 30 is provided on the substrate 22, and a first conductive layer, typically polysilicon, is deposited and patterned to define the bottom capacitor electrode 24. A layer of dielectric is deposited over the bottom electrode to provide the capacitor dielectric 28. A second conductive layer, such as polysilicon, is deposited thereon to define the top capacitor electrode 26.
As is readily apparent, the amount of surface area utilization is substantially affected by the size of the capacitor plate face 32 (which in the case of the first electrode 24 is in contact with the insulation layer 30). Thus, reducing the overall size of the capacitor 20 is one way to increase overall capacitor density of an IC.
Since market forces are driving the integrated circuitry towards increasing the density of capacitors on an IC in order to maximize IC substrate surface utilization, it would be desirable to have a capacitor structure, which facilitates such increasing of capacitor density, and a method for making the same.